1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, relates to a semiconductor integrated circuit device having a capacitor portion, such as a dynamic random access memory (DRAM), capable of increasing charge storage capacitance of the capacitor portion.
2. Description of the Prior Art
In recent years, in a semiconductor integrated circuit device, particularly, in a dynamic random access memory of a single transistor and single capacitor type, as a circuit pattern is fined due to a high integration, an area for a capacitor is decreased, which causes a problem of a soft error, defective circuit margin, and the like due to decrease of charge storage capacitance in the capacitor portion. Many countermeasures have been taken so as to cope with these problems.
FIG. 1 is a diagram showing a sectional structure of a memory capacitor portion of a conventional dynamic random access memory. In FIG. 1, a thick oxide film 2 for separation between devices is formed on a P-type of silicon semiconductor substrate 1, so that adjacent devices are electrically insulated from each other. The dynamic random access memory includes at least one transistor portion and at least one capacitor portion. The transistor portion includes an N.sup.+ diffused layer 6 to be source and drain formed in a predetermined region on the P-type of semiconductor substrate 1 and a gate electrode 4 formed in a gate area of the P-type of semiconductor substrate 1 through a thin oxide layer 3. On the other hand, the capacitor portion includes the P-type of semiconductor substrate 1, the thin oxide layer 3 for storing an electric charge indicative of information, and a capacitor electrode 5 formed on a predetermined region over the thin oxide layer 3.
Writing and reading of a storage charge (information) are made in response to a voltage applied to the gate electrode 4, in which case the N.sup.+ diffused layer 6 for the source and drain serves as a path for the storage charge.
In the above described structure, if and when a circuit pattern is further fined, it is clear that the area for capacitor decreases and hence the charge storage capacitance in the capacitor also decreases. In order to prevent such decrease of the storage capacitance, it may be considered that the thickness of a thin oxide film 3 is made thinner so that the storage capacitance can be increased. However, in such a case, there is a limit that the thickness of the oxide film 3 can be made further thinner, due to limit of the breakdown voltage and the like of the gate oxide film.
Therefore, in order to increase capacitance, as shown in the dotted line in FIG. 1, it has been attempted that the P.sup.+ type of semiconductor layer 7 having high impurity concentration is formed in the silicon semiconductor substrate 1 so that the p-n junction is formed between the thin oxide film 3 and P.sup.+ type of layer 7, thereby to increase a charge storage capacitance. However, even in such a structure, if and when the area for capacitor decreases, the area of the p-n junction also decreases, and hence much more increase of charge storage capacitance can not be expected.
In order to eliminate the defect of the above described structure, the approach for increasing storage capacitance has been made by forming a deep groove in a semiconductor substrate for forming a capacitor. Such a concept is described by H. Sunami et al., "A CORRUGATED CAPACITOR CELL (CCC) FOR MEGABIT DYNAMIC MOS MEMORIES", IEDM'82 Digest, p806-808.
FIG. 2 is a drawing showing a sectional structure of a conventional improvement of a memory capacitor portion of a dynamic random access memory. Referring to FIG. 2, such structure will be described. First of all, a deep groove is formed in a region of a P-type of silicon semiconductor substrate 1, which corresponds to the area to be a capacitor, and then, the substrate 1 and the surface of the groove are covered with a thin oxide film 3. Thereafter, the groove is filled with a polycrystal silicon layer 8, for example, so that a capacitor electrode 5 is formed on an area on the groove. Accordingly, the polycrystal silicon layer 8 serves as a capacitor electrode. In such a structure, since a deep groove is formed in the substrate 1, the surface area of the groove also serves as the area for capacitor and hence the total area for capacitor can be increased. However, even in such a case, due to a breakdown voltage of a thin oxide film 3 formed on the surface of the groove, the thickness of the oxide film 3 should be made thicker than a thickness of a usual oxide film. Therefore, even if a relatively deep groove is formed so that the surface area is increased, it was still difficult to fully increase charge storage capacitance.
As described in the foregoing, mere reliance on the conventional structure can not fully compensate for decrease of charge storage capacitance accompanied by decrease of capacitor area due to a further fining of a circuit pattern.